The present invention relates generally to a Viterbi equalizer and in particular to a tap-selectable Viterbi equalizer.
Viterbi equalizers are used for decoding intersymbol interference channels for digital communication. In decoding an intersymbol interference channel, maximum likelihood sequence estimation, implemented with a Viterbi equalizer, has a significant performance gain compared to other detection techniques. However, the implementation complexity of maximum likelihood sequence estimation is generally larger than other detection techniques, and the increase in complexity could present a challenge for low-power and high-speed implementation. It is therefore desirable to reduce the implementation complexity of the Viterbi equalizer at the expense of a reasonable, preferably negligible, performance loss compared to maximum likelihood sequence estimation.
A Viterbi equalizer implements the maximum likelihood sequence estimation with a recursive approach. The transmitted symbols a1, a2 . . . an are sent through a time dispersive channel, which can be modeled as a tapped delay line with coefficients h1, h2 . . . hL. The k'th signal-value out of the channel are given as
                              r          k                =                                                            ∑                L                                            i                =                1                                      ⁢                                          h                i                            ⁢                              a                                  k                  -                  i                                                              =                                                    h                1                            ⁢                              a                k                                      +                                          h                2                            ⁢                              a                                  k                  -                  1                                                      +            …            ⁢                                                  +                                          h                L                            ⁢                              a                                  k                  -                  L                  +                  1                                                                                        (        1        )            Here, ak is the current symbol and ak−1 . . . ak−L+1 are the previous symbols.
The state is defined as the set of previous symbols [ak−1 . . . ak−L+1] which are currently in the delay line, and this set has length L−1. Since each symbol can take X possible values, the total number of possible states is given as XL−1. All the possible transitions between all the states from the previous symbol k−1 (originating state) to the current symbol k (destination state) form a state trellis with XL−1 states.
The complexity of the Viterbi equalizer, in other words the number of states in the trellis, which shows the transition from multiple previous states to multiple current states, is given as a symbol alphabet raised to the length of the channel memory minus one. This length is equal to XL−1, where X is number of different characters per symbol and L the number of symbols in a trellis code. Within an environment with X=2, such as a direct digital representation in which one character, for example “−1”, represents a digital zero and one character, for example “1”, represents a digital one, the complexity is limited and channel lengths of up to 5 symbols will not cause a big burden on a signal processor. However, faster standards require more different characters per symbol. For example, X=8 could be a possible number of characters per symbol in a high-speed application. Other higher numbers for X are possible to increase transmission speed. As can be readily seen, for example, with X=8, the number of states increases dramatically.
A delayed decision feedback sequence estimator (DDFSE) is a technique to reduce the number of states in the trellis by detecting the older symbols in the tapped delay line. However, the DDFSE can give poor performance in cases where the channel energy extends outside the DDFSE memory. One way to combat this problem is by applying pre-filtering which results in a minimum-phase system. However, this creates additional noise and computational load and may result in numerical instability.
It is desirable to provide a Viterbi equalizer that reduces the complexity of processing power without the disadvantages of the prior art.